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Fan-Out Wafer Level Packaging

Fan-Out Wafer Level Packaging

With Apple and its A10 processor employing TSMC’s InFO-PoP technology, the fan-out market has exploded. Apple’s involvement will undoubtedly generate increased interest in the fanout platform, and market revenue is forecast to reach around US$2.5B in 2021, with 80% growth between 2015 - 2017 (See Yole Développement’s August 2016 report, Fan-out: Technology & Market Trends 2016). Moreover, following the high-volume adoption of InFO and the further development of fan-out wafer level packaging technologies, a wave of new players may enter the market. The supply chain is also expected to evolve, with a considerable amount of investment in Fan-Out packaging capabilities.

In such a fast-growing Fan-Out market, it is essential to deeply understand the global patent landscape in order to anticipate changes, harvest business opportunities, mitigate risks, and make strategic decisions in order to strengthen one’s market position and maximize return on one’s IP portfolio.

Knowmade has thoroughly investigated the Fan-Out packaging patent landscape (chip-first, chip-last, face-down, face-up, single-die, multi-chip module, package-on-package, system-inpackage, etc.), and this report contains detailed patent analyses including countries of filing, patents’ legal status, and patented technologies, as well as patent owners, their IP position, and IP strategies.

More than 3,100 patents relating to over 1,200 inventions on Fan-Out packaging have been published worldwide through September 2016, coming from 100+ patent applicants. A first wave of patent applications occurred from 1999-2006, induced by Infineon. Patent applications have increased since then, with Freescale (NXP), STATS ChipPAC (JCET), SPIL, Amkor, and TSMC entering the Fan-Out IP arena. Today the number of enforceable patents is increasing worldwide, with several companies already standing out by virtue of their strong IP position.

All of major players involved has filed patents on Fan-Out packaging, except for Nanium, which does not file any patents at all but instead has adopted a different IP strategy that we discuss in this report. Another special case is the presence of patent licensing companies like Polaris Innovations (WiLAN), which in 2015 acquired key patents from Infineon/Qimonda. The visibility of such companies in the patent landscape is a tangible sign of the market explodes. In the next few years Polaris Innovations could assert its patents to make money, and in this report we present its most critical patents. We have also noted Samsung’s conspicuou IP presence in the FOWLP patent landscape, despite the company’s unclear market position. R&D labs are also present (i.e. Fraunhofer, A*STAR, CEA), but to a lesser extent. Most new entrants in the FOWLP patent landscape are Chinese players (HuaTian Technology, NCAP, SMIC), and more recently we have observed Apple’s appearance. Apple, which this year chose TSMC’s InFO-PoP technology for its A10 APE, has recently filed some patents on Fan-Out wafer level packaging (chip-last, chip-first, PoP, and SiP), reflecting a genuine interest in the FOWLP platform.

Scope of the report
Key features of the report
Objectives of the reports
Time evolution of patent applications
Major offices of patent applications
Time evolution of patent applications by country
Main patent assignees
Industry supply-chain
Technology history
Time evolution of main patent assignees
Acceleration of main patent assignees
Countries of priority patents for patent assignees
Countries of patent filings for patent assignees
Legal status of patents for main patent assignees
Remaining lifetime of granted patents
Geographic map of granted patents and pending patent applications
Countries of granted patents and pending patent Applications for main patent assignees
IP collaboration network
Main patent transactions
Licensing agreements
IP competitors dependency by patent citations
Most cited patents
Granted patents near expiration date
IP specialization degree
Prior art strength index
IP leadership
IP blocking potential
IP enforcement potential
The best IP positions
Summary of patent portfolios
Comparison of patent portfolios of the main IDMs, Foundries and OSATs PATENT LITIGATIONS
For each segment: number of patents, time evolution of patent publications and main patent assignees, Matrix of patent assignees vs. technical segments, Matrix of technology vs. process steps & technical challenges/architecture, Matrix of main patent applicants vs. technical segments
Solutions found in patents to solve warpage and die shift issues
Infineon, NXP/Freescale, STATS ChipPAC, TSMC, ASE, Deca Technologies, Nepes, Nanium, SPIL, Amkor, Powertech Technology, Intel, STMicroelectronics, Samsung, NCAP, WiLAN, 3D PLUS, Apple. Each IP profile includes: time evolution of patent applications, world map of granted patents and pending patent applications, key features and strength of patent portfolio.

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