STUDY GOALS AND OBJECTIVES

Good fences make good neighbors—especially when the available real estate is limited. For more than 30 years, silicon dioxide (SiO₂) has been the versatile dielectric "fence" material of choice for the semiconductor device industry, providing adequately high-capacitance gate insulation at the front end of the line and sufficiently low-k, crosstalk-free insulation between interconnect wiring levels at the back end. Now, thanks to scaled-down chip components, more densely populated chip real estate, and the introduction of low-resistance interconnect materials like copper, the industry's familiar, reliable SiO₂ "fencing" may no longer be good enough for either application.

This comprehensive BCC study reports on the industry's current "fence-mending" work to meet the growing dielectric materials challenges:

• Low- and ultra low-k solutions in the low-k arena, including porous and nonporous, organic and inorganic compounds for interlayer and intermetal applications.
• High-k candidates, ranging from nitrided silicon oxide through simple metal and rare-earth oxides to ferroelectric materials for gate dielectric and super-dense gigabit memory devices.
• The cost- and technology-based requirements for these new materials and the additional challenge of integrating them into the wafer fabrication processes.

The report also discusses low- and high-k dielectric market opportunities by providing:

• Forecasts for materials and equipment, including both spin-on and chemical vapor deposition tools for interlayer dielectric application.
• Dielectric-focused profiles of major chip makers, materials suppliers, and equipment manufacturers.
• A detailed analysis of U.S. patents issued since 1996 for new dielectric materials, processes, and semiconductor-related applications.

REASONS FOR DOING THE STUDY

Since the introduction of the transistor, the semiconductor industry has seen an unprecedented rate of change in manufacturing productivity and device performance. Much of this advancement is based on two major pillars: the intrinsic properties and integration capability of silicon and the scalability of the MOSFET with silicon as the substrate and silicon dioxide as an insulator. Now, after 30 years of decreasing size and increasing performance, traditional scaling is nearing fundamental limits at the 130 nm feature size. This BCC study explores the emerging opportunities for the chemical and equipment manufacturers of the new materials and process tools required for continued improvement in electrical performance and additional scaling, down to 100 nm and below, in the near term.

CONTRIBUTIONS OF THE STUDY AND FOR WHOM

This report analyzes market segments of the semiconductor industry related to the development and integration of dielectric materials into the manufacturing process for microprocessors (MPUs), dynamic memory (DRAM), and a range of current and emerging technologies, such as system-on-a-chip (SOC) and silicon-on-insulator (SOI). The industry sectors covered include device manufacturers as well as materials and equipment providers, with company profiles and discussions of future research, development, and engineering.

The work is directed to decision makers in the covered sectors, including:

• Suppliers of dielectric and silicon-replacement materials
• Semiconductor device designers and fabricators
• Material deposition, planarizing, cleaning, and testing equipment manufacturers
• Marketplace managers
• Merger, acquisition, and investment executives

SCOPE AND FORMAT

This report is an analytical business tool whose primary purpose is to understand the markets for dielectric materials and process equipment for their application. It includes the following sections:

• A summary of the dielectric material and process tool market (Executive Summary).
• An industry overview discussing types of dielectric materials and their integration into the manufacturing process (Dielectrics Overview).
• Analyses of current and future markets for dielectric materials and associated process equipment in the U.S. and globally (Market Analysis).
• Overview and analysis of future directions and timelines for comprehensive development and integration of new materials and processes into functioning production lines (Great Expectations).
• A detailed patent analysis covering U.S. patents issued after 1996 for dielectric materials and dielectric-related processes for the semiconductor industry (patent analysis).

METHODOLOGY AND INFORMATION SOURCES

The material presented is based on information gathered from personal contacts with participants within the equipment and materials industry as well as a thorough review of the technology gathered from technical papers and industry conferences. The final analyses and projections are based on a combination of a consensus among the primary contacts combined with an understanding of the impact of trends from a historical perspective.

Additional data was obtained from extensive reviews of secondary sources. These include trade publications, trade associations, company literature, and on-line databases. This was done to supplement understanding of applications, markets, and trends in the semiconductor device industry. All dollar projections presented in this report are in 2000 constant dollars.

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