Read Architectures for Multi-bit per cell NAND Flash Memories

Published by: Forward Insights

Published: Sep. 1, 2009 - 36 Pages

Table of Contents

Contents

CONTENTS

LIST OF FIGURES

EXECUTIVE SUMMARY

INTRODUCTION

NAND FLASH READ ARCHITECTURES

Conventional Read Architecture

Latch design

All Bitline Sensing (ABL) Architecture

Sensing Design

ABL Sensing vs. Conventional Read

Summary

REFERENCES

ABOUT THE AUTHOR

ABOUT FORWARD INSIGHTS

Services

Contact

REPORT OFFERINGS

List of Figures

Figure 1. NAND Architecture

Figure 3. Conventional Read: Essential Elements of the Page Buffer

Figure 4. Conventional Read Timing

Figure 5. Conventional Read Latches

Figure 6. Conventional Read: Latch characteristic for appropriate sizing

Figure 7. ABL sensing: Essential Elements of the Page Buffer

Figure 9. ABL sensing: the sense

Figure 10 Evaluation Time

Figure 11. Contributors to Parasitic Capacitance (Bitline cross-section)

Figure 12 Three adjacent bitlines and the effect of capacitive coupling between them

Figure 13 Yupin Effect

Figure 14. Cell working points

Figure 17 Programming Time for 2-bit/cell NAND Flash Memory

Figure 19 Energy Savings

Figure 20 3-bit/cell ABL Programming

List of Tables

Table 1. ABL vs. Conventional Read Architecture

Abstract

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