Key NAND Flash Memory Design Intellectual Property

Published by: Forward Insights

Published: Jul. 1, 2009 - 152 Pages

Table of Contents

Contents

Contents

List of Figures

Methodology

Issues Inherent in Multi-state NAND Flash Memory

Key NAND Flash Intellectual Property

Sensing Architecture for Multi-state Memories

U.S. Patent No.

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Source Voltage Noise Compensation

US Patent Application No.

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Coarse and Fine Programming

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Sequential page programming

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Floating Gate-Floating Gate Noise Coupling Reduction and Background Pattern Dependency

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U.S. Patent Application No.

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Sensing and Page Buffer Improvements

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Negative Threshold Sensing

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Program Disturb

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Temperature Compensation

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High Voltage Switch

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Charge Pumps

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Coding Schemes and Error Correction Codes

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U.S. Patent Application No.

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U.S. Patent No. .156

U.S. Patent Application No.

References

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List of Figures

Figure 1 NAND Architecture: 1-bit/cell storage

Figure 2 NAND Architecture: from 1-bit/cell to 4-bit/cell storage

Figure 3 ID vs. VCG for four different charges Q1-Q4

Figure 4 Memory device

Figure 5 NAND programmed distribution width: Contributors

Figure 6 Generic memory device

Figure 7 Symmetrical memory device

Figure 8 Source bias errors

Figure 9 Threshold voltage shift of a memory cell caused by a source line voltage drop

Figure 10 Example of how a read can fail due to source line bias error

Figure 11 A flow diagram showing a multi-pass sensing method for reducing source line bias

Figure 12 Schematic diagram illustrating a multi-pass sense module

Figure 13 Flow diagram showing the operation of the multi-pass sense module

Figure 14 Three adjacent bit lines and the effect of capacitive coupling between them

Figure 15 Flow diagram showing a method of sensing while reducing bit-line to bit-line coupling 33

Figure 16 Flow diagram showing a more detailed embodiment of the sensing step 530

Figure 17 Sense module implementing all bit line sensing

Figure 18 Timing diagrams

Figure 19 Method of program and read reducing neighboring floating gate coupling

Figure 20 Flow diagram showing a preferred embodiment of the inventive step

Figure 21 Memory array organized into a left page and a right page

Figure 22 A process for biasing a substrate with a voltage which is a function of a source voltage . 50

Figure 23 A process for compensating a control gate voltage with a voltage which is a function of

a source voltage

Figure 24 A process for compensating a bit line voltage with a voltage which is a function of a

source voltage

Figure 25 A process for compensating a forward body bias with a voltage which is a function of a

source voltage

Figure 26 Example of an array of storage elements, where body bias is compensated based on a

source voltage

Figure 27 Example of an implementation of the compensation/erase circuits

Figure 28 Example of an array of storage elements, where a control gate voltage is compensated

based on a source voltage

Figure 29 Example of an array of storage elements, where a bit line voltage is compensated based

on a source voltage

Figure 30 Conventional WL, BL and SL voltage control referencing from the same ground of the

IC memory chip

Figure 31 BL and WL voltage having a reference point at the node where cell source signal

accesses the source lines

Figure 32 BL and WL voltage having a reference point at the selected page source line

Figure 33 Tracking bit line voltage control circuit

Figure 34 Tracking word line voltage control circuit

Figure 35 Changing threshold value of memory cells of a known flash memory

Figure 36 Changing threshold value of a memory cell according to the invention

Figure 37 The signal waveforms in a write step of the first and second embodiment

Figure 38 Order in which data is written into a memory cell for 3 bit/cell storage

Figure 39 Relationship between the data in a memory cell and the threshold voltages for 3-bit/cell

storage

Figure 40 Steps of new program technique

Figure 41 Flow diagram minimizing the coupling errors

Figure 42 BLX generator

Figure 43 All Bit Line Sensing

Figure 44 Strobe generator

Figure 45 Programming of a non-volatile storage element for 3-bit/cell storage

Figure 46 Configuration of a NAND string and components for sensing

Figure 47 Voltage drop with time for different lines of fixed current

Figure 48 Waveforms associated to current sensing for negative current sensing

Figure 49 Associated sensing process

Figure 50 Bouncing of source line voltage and flow chart

Figure 51 Components of current sensing with biasing of Source and P-Well

Figure 52 Source Bias All Bit Line Sensing scheme

Figure 53 Source Bias All Bit Line Sensing scheme when sensing occurs

Figure 54 Waveforms associated with Source Bias All Bit Line Sensing

Figure 55 Sensing process associated with Source Bias All Bit Line Sensing

Figure 56 NAND string and components for temperature-compensated sensing

Figure 57 Voltage-temperature dependency

Figure 58 Waveforms associated with current sensing with T compensation

Figure 59 Associated Sensing and Erase Flow

Figure 60 Programming Stress

Figure 61 Programming and reading operations at the same temperature

Figure 62 Programming at a high temperature and reading at a low temperature

Figure 63 Programming at low temperature and reading at high temperature

Figure 64 Threshold distribution profile spread due to temperature threshold shift

Figure 65 Temperature-compensated read voltage generator using a dummy cell

Figure 66 Temperature-compensated read voltage generator using a MOS

Figure 67 Voltage generator

Figure 68 Current generators

Figure 69 Band gap reference circuit

Figure 70 Read/verify voltage generator

Figure 71 Constant reference voltage V1

Figure 72 Flexible (temperature-dependent) reference voltage V2

Figure 73 Relationship between drain-to-source current Ids and gate voltage Vg

Figure 74 Temperature dependent voltage generator

Figure 75 High voltage switching circuit

Figure 76 High Voltage Switch boosting based

Figure 77 Timing diagram

Figure 78 High Voltage switch doubler-based

Figure 79 Multi stage High Voltage switch doubler-based

Figure 80 Voltage adder stages

Figure 81 Voltage adder stages plus doubler stages

Figure 82 Alternative voltage adder stages plus doubler stages

Abstract

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