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Published by: IEC
Published: May. 1, 2008 - 544 Pages
Table of Contents
- Part I
- Chapter 1: Power Supply Compensation for Capacitive Loads
- Jonathan L. Fasig, Principal Engineer, Mayo Clinic
- Barry K. Gilbert, Director, Mayo Clinic
- Erik S. Daniel, Deputy Director, Mayo Clinic
- 1.1: Abstract
- 1.2: Introduction
- 1.3: System Overview
- 1.4: Power Supply Stability Primer
- 1.5: Analysis
- 1.6: Conclusion
- Chapter 2: DC-DC Converters: What is Wrong with Them?
- Istvan Novak, Senior Signal Integrity Staff Engineer, Sun Microsystems
- 2.1: Abstract
- 2.2: Introduction
- 2.3: DC-DC Converter Parameters Related to Signal Integrity
- 2.4: Potential SI Problems from the User's Perspective
- 2.5: Conclusion
- Chapter 3: The Advantage of Controlled-ESR Polymer Capacitators
- Hideki Ishida, Design and Application Section Manager, Sanyo Electric Co.
- 3.1: Abstract
- 3.2: Controlling ESR Value of Tantalum Polymer Capacitor
- 3.3: Importance of Controlled ESR Value Capacitor
- 3.4: Tantalum Polymer Capacitor with DC/DC Converter Switching in the MHz Range
- 3.5: Equivalent Circuit of Polymer Tantalum Capacitor
- Chaper 4: ESR-Controlled MLCCs and Decoupling Capacitor Network Design
- Masaaki Togashi, Senior Development Engineer, TDK Corp.
- Chris Burket, Senior Applications Engineer, TDK Corp.
- 4.1: Abstract
- 4.2: Introduction
- 4.3: Decoupling Capacitor Network
- 4.4: ESR and ESL
- 4.5: ESR Control Method
- 4.6: ESR/ESL Measurement of MLCCs
- 4.7: Measurement Results
- 4.8: Circuit Analysis using SPICE Simulation
- 4.9: Lower ESL Development
- 4.10: Conclusion
- Part II
- Chapter 5: A Power Distribution System
- K. Barry A. Williams, Principal Engineer, Hewlett-Packard
- 5.1: Abstract
- 5.2: An Example of a Power Distribution Design System
- 5.3: The Problem Schematic
- 5.4: The Characterization of the Load
- 5.5: System Bandwidth
- 5.6: Determination of the Maximum Impedance
- 5.7: The Q of the System
- 5.8: Capacitance and Inductance Determination
- 5.9: Resonant Frequency Points
- 5.10: Number of Capacitors
- 5.11: Summary of Compiled Results
- 5.12: Summary of the Capacitor Selections and Graphical Selections
- 5.13: Graphics Results with Added Resistance
- 5.14: Sensitivity
- 5.15: Summary of the Design
- Chapter 6: Designing Minimum Cost VRM8.2/8.3 Compliant Converters
- Richard Redl, President, ELFI S.A.
- Brian Erisman, Project Engineer, Analog Devices, Inc.
- 6.1: Abstract
- 6.2: Introduction
- 6.3: Objective Specifications
- 6.4: Load Transient Performance Limits of the Buck Converter
- 6.5: Optimal Load Transient Response
- 6.6: Commonly Used Control Techniques
- 6.7: Design for Optimal Output Impedance
- 6.8: Computer Simulations and Experimental Results
- 6.9: Summary
- Chapter 7: Frequency Domain Target Impedence Method for Bypass Capacitator Selection for Power Distribution Systems
- Larry D. Smith, Principal Signal Integrity Engineer, Altena Corp.
- 7.1: Abstract
- 7.2: Introduction
- 7.3: Target Impedance
- 7.4: Impedance in the Frequency Domain
- 7.5: PCB Bypass Capacitor
- 7.6: Capacitor Sizing from Target Impedance and Corner Frequency
- 7.7: ESR Considerations
- 7.8: Problems at High and Low Frequency
- 7.9: Comparing FDTIM to Other Methods
- 7.10: Conclusion
- Chapter 8: Resonant-Free Power Network Design Using Extended Adaptive Voltage Positioning Methodology
- Alex Waizman, Principal Engineer, Intel Corp.
- Chee-Yee Chung, Principal Engineer, Intel Corp.
- 8.1: Abstract
- 8.2: Introduction
- 8.3: Lumped Power Delivery Model
- 8.4: Adaptive Voltage Positioning
- 8.5: EAVP
- 8.6: Time Domain Results
- 8.7: Future Work
- 8.8: Summary
- Chapter 9: Distributed Matched Bypassing for Board-Level Power Distribution Networks
- Istvan Novak, Senior Staff Engineer, Sun Microsystems
- Leesa Noujeim, Staff Engineer, Sun Microsystems
- Valerie St. Cyr, Supply Base Development Manager, Sun Microsystems
- Nick Biunno, Principal Engineer, Sanmina-SCI
- Atul Patel, Process Engineer, Sanmina-SCI
- George Korony, Senior Member of Technical Staff, AVX Corp.
- Andy Ritter, Senior Member of Technical Staff, AVX Corp.
- 9.1: Abstract
- 9.2: Introduction
- 9.3: Distributed Matched Bypassing of Power Distribution Networks
- 9.4: Implementation of Distributed Matched Bypassing
- 9.5: The Concept of the Bypass Resistor
- 9.6: Conclusion
- Part III
- Chapter 10: Comparison of Power Distribution Network Design Methods: An Approach to System-Level Power Distribution Analysis
- Dale Becker, Senior Technical Staff Member, IBM Corp.
- 10.1: Abstract
- 10.2: Introduction
- 10.3: A Computer System
- 10.4: Power Distribution Noise Analysis
- 10.5: Summary
- Chapter 11: Bypass Filter Design Considerations for Modern Digital Systems, a Comparative Evaluation of the Big ""V,"" Multipole, and Many Pole Bypass Strategies
- Steve Weir, Consultant, Teraspeed Consultant Group
- 11.1: Abstract
- 11.2: What Does the Bypass Network Do?
- 11.3: Multilayer Chip Capacitor Bypass Basics
- 11.4: Bypass Strategies--Three Methods, Three Faiths?
- 11.5: Summary
- 11.6: Conclusion
- Chapter 12: Comparison of Power Distribution Network Design Methods: Bypass Capacitator Selection Based on Time Domain and Frequency Domain Preferences
- Istvan Novak, Senior Signal Integrity Staff Engineer, Sun Microsystems
- 12.1: Abstract
- 12.2: Introduction
- 12.3: So, What Is the Metric?
- 12.4: Comparison of Popular Methods Based on Lumped Self-Impedance
- 12.5: Component Placement
- 12.6: Implementation Examples
- 12.7: Conclusion
- Chapter 13: PDN Design Strategies: Ceramic SMT Decoupling Capacitators--What Values Should I Choose?
- James L. Knighten, Senior Staff Engineer, NCR Corp.
- Bruce Archambeault, Distinguished Engineer, IBM
- Jun Fan, Senior Hardware Engineer, NCR Corp.
- Giuseppe Selli, Ph.D. Candidate, University of Missouri-Rolla
- Samuel Connor, Senior Engineer, IBM
- James L. Drewniak, Professor, University of Missouri-Rolla
- 13.1: Introduction
- 13.2: The Power Bus Function
- 13.3: The Decoupling Capacitor
- 13.4: Interconnect Inductance
- 13.5: Conclusion
- Part IV
- Chapter 14: Power Integrity Analysis of DDR2 Memory Systems during Simultaneous Switching Events
- Ralf Schmitt, Signal Integrity Engineer, Rambus, Inc.
- Joong-Ho Kim, Signal Integrity Engineer, Rambus, Inc.
- Chuck Yuan, Signal Integrity Engineer, Rambus, Inc.
- June Feng, Signal Integrity Engineer, Rambus, Inc.
- Woopoung Kim, Signal Integrity Engineer, Rambus, Inc.
- Dan Oh, Signal Integrity Engineer, Rambus, Inc.
- 14.1: Abstract
- 14.2: Introduction
- 14.3: Supply Noise Modeling Methodology for Interface Systems
- 14.4: SSN Model for DDR2 Test System
- 14.5: Determining Worst-Case Switching Profiles
- 14.6: Correlating Supply Noise Parameters
- 14.7: Measuring Supply Noise on Internal Supply Voltage
- 14.8: Summary
- Chapter 15: Analysis of Supply Noise Induced Jitter in Gigabit I/O Interfaces
- Ralf Schmitt, Signal Integrity Engineers, Rambus, Inc.
- Hai Lan, Signal Integrity Engineer, Rambus, Inc.
- Chris Madden, Signal Integrity Engineer, Rambus, Inc.
- Chuck Yuan, Signal Integrity Engineer, Rambus, Inc.
- 15.1: Abstract
- 15.2: Introduction
- 15.3: Power Supply Design Environment Requirements for Gigabit I/O Interfaces
- 15.4: Overview of Gigabit I/O Interface Test System
- 15.5: Measurement of Supply Noise–Induced Jitter in a Gigabit I/O Interface
- 15.6: Summary
- Chapter 16: PCB Design Methods for Optimum FPGA SerDes Jitter Performance
- Steve Weir, Consultant, Teraspeed Consulting Group
- Steve McMorrow, President, Teraspeed Consulting Group
- Al Neves, Consultant, Teraspeed Consulting Group
- Tom Dagostino, Vice President, Teraspeed Consulting Group
- Brian Vicich, Signal Integrity Engineer, Samtec, Inc.
- 16.1: Abstract
- 16.2: FPGA SerDes Design Challenge
- 16.3: Virtex 4TM Rocket I/O Transmitter
- 16.4: MGT PDN PCB Reference Model
- 16.5: Linear Regulator Ripple Regulator
- 16.6: Jitter Evaluation Test Vehicle
- 16.7: Jitter Evaluation Tests
- 16.8: Summary
- 16.9: Conclusion
- Chapter 17: Power Distribution System Design
- Mark Alexander, Senior Staff Engineer, Xilinx, Inc.
- 17.1: Abstract
- 17.2: Required PCB Decoupling Capacitors
- 17.3: Basic Decoupling Network Principles
- 17.4: Role of Inductance
- 17.5: Simulation Methods
- 17.6: PDS Measurements
- 17.7: Optical Decoupling Network Design
- 17.8: Other Concerns and Causes
- Part V
- Chapter 18: Aperiodic Resonant Excitation of Microprocessor Power Distribution Systems and the Reverse Pulse Technique
- Victor Drabkin, Senior Member of Technical Staff, Hewlett-Packard
- Chris Houghton, Senior Member of Technical Staff, Hewlett-Packard
- Isaac Kantorovich, Senior Member of Technical Staff, Hewlett-Packard
- Michael Tsuk, Senior Member of Technical Staff, Hewlett-Packard
- 18.1: Abstract
- 18.2: Introduction
- 18.3: Definitions
- 18.4: Reverse Pulse Technique--Plausible Reasoning
- 18.5: Reverse Pulse Techniques--Proof
- 18.6: Development
- 18.7: Conclusion
- Chapter 19: Modeling Noise on Printed Circuit Board Power Planes
- John Grebenkemper, Ph.D., Development Engineering Manager, Hewlett-Packard
- 19.1: Abstract
- 19.2: Introduction
- 19.3: Phases of Power Plane Phase
- 19.4: Methods to Predict Noise
- 19.5: Noise Prediction Method
- 19.6: Noise Control Methods
- 19.7: Bypass Capacitor ESR
- 19.8: Measurement of Bypass Capacitors
- 19.9: Conclusion
- Chapter 20: Toward Developing a Standard for Data Input/Output Format for PDN Modeling and Simulation Tools
- Ravi Kaw, Senior Staff Engineer, Agilent Technologies, Inc.
- Istvan Novak, Senior Staff Engineer, Sun Microsystems
- Madhawan Swaminathan, Professor, Georgia Institute of Technology
- 20.1: Abstract
- 20.2: Introduction
- 20.3: PDN Classification
- 20.4: IO PDN + SDN
- 20.5: Desirable Common Features for Both PDNs
- 20.6: Proposed Requirements for Modeling Tools
- 20.7: Proposed Requirements for Simulation Tools
- 20.8: Methodology
- 20.9: Standards
- 20.10: Conclusion
- Chapter 21: Overview of Frequency Domain Power Distribution Measurements
- Istvan Novak, Senior Signal Integrity Staff Engineer, Sun Microsystems
- 21.1: Abstract
- 21.2: Why Frequency Domain?
- 21.3: How to Measure PDN Impedance
- 21.4: Extracting Component Values
- 21.5: Calibration and Probes
- 21.6: Making the Proper Connections
- 21.7: Measuring Full PDN
- 21.8: Repeatability of Data
- Chapter 22: Simple Transmission Line Causal Model for Multilayer Ceramic Capacitators
- Istvan Novak, Senior Staff Engineer, Sun Microsystems
- Gustavo Blando, Staff Engineer, Sun Microsystems
- Jason R. Miller, Senior Staff Engineer, Sun Microsystems
- 22.1: Abstract
- 22.2: Introduction: Present Modeling Options
- 22.3: Periodically Loaded Causal Transmission-Line Model
- 22.4: Conclusion
Abstract"Power Distribution Network Design Methodologies" is a collection of cogently written articles by 49 industry experts that fills in the void on PDN design procedures, and addresses among others such related topics as DC-DC converters, selection of bypass capacitors, DDR2 memory systems, powering of FPGAs, synthesis of impedance rofile. Through each of these contributions from such leading companies as SUN Microsystems, Sanyo, IBM, Hewlett-Packard, Intel, and Rambus, the reader can come to understand why books on power-integrity are only now becoming available to the public and can relate these topics to current industry trends.
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