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Published by: IEC
Published: Mar. 1, 2008 - 483 Pages
Table of Contents
- Part I: Overview
- Chapter 1: Introduction
- Brian Bailey, Proprietor, Brian Bailey Consulting
- Kathy Werner, IP Strategic Business Manager, Freescale Semiconductor; President, VSI Alliance
- 1.1: Introduction
- 1.2: Historical Overview
- 1.3: Business Models
- 1.4: Who Should Read This Book?
- 1.5: The Book’s Structure and How to Read It
- 1.6: Chapter Listing
- Chapter 2: The Business of SIP
- Jack Horgan, Managing Editor, EDACafe
- 2.1: Introduction
- 2.2: Value Proposition
- 2.3: Market Size
- 2.4: How to Find IP Vendors
- 2.5: Publicly-Traded Companies
- 2.6: The Big Three EDA Companies
- 2.7: Privately-Held Companies
- 2.8: Non-SIP Companies
- 2.9: Entering the IP Market
- Chapter 3: Building a Legally Sound Intellectual Property Portfolio
- Dennis Fernández, Managing Partner, Fernández & Associates, LLC
- Behfar Bastani, United States Patent Agent
- Susan Fintz, Attorney, Wilson, Sossini, Goodrich, and Rosati
- 3.1: Introduction
- 3.2: Forms of Protection
- 3.3: Design States
- 3.4: License Terms, Risks, and How to Mitigate
- Part II: The IP Provider
- Chaper 4: Analog, Star, and Commodity IP Blocks
- Henry Chang, Vice President and Co-Founder, Designer’s Guide Consulting
- Larry Cooke, Engineering Consultant
- Grant Martin, Chief Scientist, Tensilica, Inc.; Senior Member, IEEE
- 4.1: Introduction
- 4.2: Analog IP
- 4.3: Star IP
- 4.4: Commodity IP
- 4.5: Emerging Issues
- Chapter 5: IP Protection
- Saverio Fazzari, Associate, Booz Allen Hamilton
- 5.1: Introduction
- 5.2: Why Protect IP?
- 5.3: History of IP Protection
- 5.4: EDA and IP Protection
- 5.5: Different Technical IP Protection Methods
- 5.6: Legal IP Protection Issues
- 5.7: Different IP Types
- 5.8: Challenges for Successful IP Protection
- 5.9: Future of IP Protection
- Chapter 6: Software
- Richard Vlamynck, Verification Engineer, Mentor Graphics Corp.
- 6.1: Introduction
- 6.2: Software Considerations for Hardware IP
- 6.3: The Fundamental Problems of Software Drivers for Hardware IP
- 6.4: Binaries versus Source Code
- 6.5: Software Verification and Debug
- 6.6: Conclusion
- Chapter 7: Verification IP
- Sean Smith, Chief Verification Architect, Denali Software
- 7.1: What is Verification IP?
- 7.2: Benefits of IP
- 7.3: Make versus Buy
- 7.4: Evolution of Verification IP
- 7.5: Architecture of Modern VIP
- 7.6: Future VIP Directions
- 7.7: Checklists for Evaluating VIP
- 7.8: Summary
- Chapter 8: Verification of IP
- Leena Singh, Senior Staff Manager and Engineer, Qualcomm, Inc.
- 8.1: Introduction
- 8.2: Challenges in Verifying IP and Industry Trends
- 8.3: Creating a Verification Environment
- 8.4: Example Implementation
- 8.5: Following Standards
- Chapter 9: IP Quality
- Kathy Werner, IP Strategic Business Manager, Freescale Semiconductor; President, VSI Alliance
- 9.1: Introduction
- 9.2: Internal IP Reuse Quality
- 9.3: Third-Party IP Quality
- 9.4: Quality Specific to IP Types
- 9.5: Future Quality Considerations
- Part III: The IP User
- Chapter 10: IP Selection
- Adam Traidman, President, Chip Estimate Corporation
- Pallab Chatterjee, Chief Technical Officer, SiliconMap, LLC
- 10.1: Introduction
- 10.2: The Process of IP Selection
- 10.3: IP Sourcing
- 10.4: Selection Criteria
- 10.5: IP Evaluation
- Chapter 11: Block-Level and Platform-Level Reuse
- Jeff Freeman, Member, Technical Staff, Transportation and Product Standard Group, Freescale Semiconductor
- 11.1: Introduction
- 11.2: Architecture
- 11.3: Block-Level Reuse
- 11.4: Platform-Level Reuse
- 11.5: Verification Reuse
- 11.6: Documentation Reuse
- 11.7: Points of View
- 11.8: Conclusion
- Chapter 12: Integration, Test, and Debug
- Neil Stollon, Principal Engineer, HDL Dynamics
- 12.1: Introduction
- 12.2: Integration Issues
- 12.3: Digital IP Integration
- 12.4: Analog IP Integration
- 12.5: Integration of Soft versus Hard IP
- 12.6: Test Issues
- 12.7: Design for Debug Issues
- 12.8: Other Related Issues
- 12.9: Conclusion
- Part IV: Case Studies
- Chapter 13: Back-End Methodology and Techniques for a Multiprotocol Mixed Signal IP Design
- Ken Umino, Consultant, Synopsys Professional Services
- Jason Upton, Synopsys Professional Services
- Ross Segelken, Design Engineer, nVidia
- John T. Stonick, Application Engineer, Synopsys Professional Services
- 13.1: Introduction
- 13.2: Basic Architecture Description
- 13.3: Sub-Block and Lane Configuration Description
- 13.4: Library Preparation Flow
- 13.5: Constraints Strategy
- 13.6: Physical Design Strategy
- 13.7: Final Remarks
- Chapter 14: eVC for Functional Simulation of Voltage/Temperature Variation and Noise on an I/O Bus
- Joseph D. Mendenhall, IBM
- Robert B. Likovich, Jr., IBM
- Chad E. Winemiller, IBM
- 14.1: Introduction
- 14.2: Problem Description
- 14.3: Selection of Verification Language
- 14.4: Elastic Interface eVC Capabilities
- 14.5: eVC Parameters
- 14.6: Resolution of eVC Parameters
- 14.7: Phase Completion Mechanism
- 14.8: Conclusion
- Chapter 15: Toward Automation of IP (Reuse) Quality Measurement
- Michael Rohleder, Principal Staff Engineer, Freescale New Product Development Center
- Ahmed Dabbagh, Design-for-Reuse Team Leader, Freescale Semiconductor
- Joachim Fader, Principal Staff Engineer, Freescale New Product Development Center
- 15.1: Introduction
- 15.2: Common Design Environment
- 15.3: Certification
- 15.4: Initial Analysis
- 15.5: Related Work
- 15.6: Simplifying Certification
- 15.7: Rule Pruning
- 15.8: Meta Pruning
- 15.9: Golden Rules
- 15.10: Automation
- 15.11: Integration and Data Integrity
- 15.12: Effort for Implementation versus Update
- 15.13: Some First Results
- 15.14: Incremental Certification
- 15.15: Rule Characterization and Classification
- 15.16: IP Reuse Quality Requires Verification IP Reuse Quality
- 15.17: Structural and Interface Requirements for VIP
- 15.18: Verification Flow Automation
- 15.19: Summary
- Chapter 16: Strategies of IP Evaluation, Selection, and 389 Management
- Mobashar Yazdani, ASIC Program Manager and Technologist, Hewlett-Packard
- Mike Stahl, Alliance Manager and Design Technology Scientist, Hewlett-Packard
- 16.1: Introduction
- 16.2: The Challenge
- 16.3: The Next Seven Years
- 16.4: Design or Buy
- 16.5: IP Life Cycle
- 16.6: IP Categorization
- 16.7: Point IP or Portfolio Assessment
- 16.8: IP Vendor/Supplier Evaluation Areas
- 16.9: IP Acquisition
- 16.10: Transferring IP
- 16.11: Summary
- Chapter 17: Considerations for ASIC Physical Design
- Ramesh Banda, Distinguished Member of Technical Staff, LSI Logic Corporation
- 17.1: Introduction
- 17.2: Front-End Design and Test Flow Diagram
- 17.3: Tools and Associated Versions Audits
- 17.4: RTL Deliverables Audits
- 17.5: RTL Audits
- 17.6: DFT/Verification Audits
- 17.7: Synthesis, Timing, and Constraints Audits
- 17.8: Front-End Flow Audits Checklist
- 17.9: Unique Features in Design Flow
- 17.10: Conclusion
- Chapter 18: Case Study, Multiformat Video Decoder IP Design Based on Configurable and Extensible Processor IP
- Gulbin A. Ezer, Hardware Design Manager, Tensilica, Inc.
- Dennis Moolenaar, Applications Engineer, Tensilica, Inc.
- 18.1: Introduction
- 18.2: Block-Based Video Decompression Algorithms
- 18.3: Architectural Evaluation Phase and IP Selection
- 18.4: Design Phase
- 18.5: MP Partition of Decoder Applications and Validation on ESL Models
- 18.6: System Emulation on FPGA Platform
- 18.7: Physical Design of Full System
- 18.8: Packing Video Decoder IP
- 18.9: Conclusion
AbstractFeaturing articles by top experts from such companies as Rambus, IBM, Hewlett-Packard, Freescale Semiconductor, and Tensilica, Inc., Intellectual Property for Electronic Systems: An Essential Introduction addresses the issues that concern those in the IP field looking to keep systems safe and secure without sacrificing quality or ease of use. The book covers verification, standards, handoff, and legal issues to create a comprehensive look at one of the most important, yet sometimes underappreciated, topics in the industry.
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