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I/O, I/O, Changing the Status Quo: Chip-to-Chip Interconnects

Published by: In-Stat

Published: Feb. 7, 2007 - 94 Pages


Table of Contents



Executive Summary

Introduction

Technology Overview of Non-Proprietary Interconnects

Comparing and Contrasting HyperTransport, PCI Express and Serial RapidIO

PCI and PCI-X

PCI Express 1.0 (1.1)

PCI Express 2.0

Formal Specifications for PCI Express 2.0

PCI-SIG Specifications Aside from PCI Express 2.0

Geneseo

Extensions to the PCI Standard

CompactPCI and PXI Standards

Molex and Quellan

PCI Express Switches and Bridges

PLX Technology, IDT, and Pericom Products

HyperTransport

The Origin of HyperTransport Through HyperTransport 2.0

HTX Connector

HyperTransport 3.0

Mobilizing the HT Consortium Membership

AMD Architecture

Torrenza

Torrenza, HyperTransport, or HTX Connector Products

RapidIO

Parallel RapidIO

Serial RapidIO

Serial RapidIO 2.0

The Rise of Serial RapidIO

Products Using RapidIO

Paradigm Shifts in Computing

Multicore Processing

The Role of FPGAs in Co-Processing

Interconnects by Application

Personal Computers

Ultra Mobile Personal Computers

Embedded PCB (Industrial PCs)

Medical Devices

Defense Industry

Supercomputers

Edge Routers and Core Routers

X86 Servers

W-CDMA (New Base Stations)

Consumer Electronics

Commercial Digital Video Recorders

Storage Area Networks

Automotive Systems

Communications Boards

Non-Proprietary I/Os Consumer Devices Using Proprietary I/O

Game Consoles

Set Top Boxes

Handheld Devices, Including Cell Phones

Broadband Customer Premise Equipment

Roll-up of Tables

Methodology

Methodology II

Related In-Stat Reports




List of Tables




Table 1. Comparison Table for HyperTransport 3.0, PCI Express 2.0, and Serial RapidIO 2.0

Table 2. Bit-Width Paths for PCI Express, HyperTransport, and Rapid IO

Table 3. Lane Iterations in PCIe Switching Products

Table 4. PLX Technology Switch and Bridge Product Family

Table 5. IDT PCI Express Switch Product Family

Table 6. Interconnections in Personal Computers (Units in Thousands)

Table 7. Interconnections in Ultra Mobile PCs (Units in Thousands)

Table 8. Interconnections in Embedded PCB Boards (Units in Thousands)

Table 9. Interconnections in Medical Devices (Units in Thousands)

Table 10. Interconnections in the Defense Industry (Units in Thousands)

Table 11. Interconnections of New Processors in Super Computers Top500 (Units in Thousands)

Table 12. Interconnections in Edge and Core Routers (Units in Thousands)

Table 13. Interconnections in x86 Servers (Units in Thousands)

Table 14. Interconnections in W-CDMA Base Stations (Units in Thousands)

Table 15. Interconnections in Consumer Electronics (Units in Thousands)

Table 16. Interconnections in Commercial Digital Video Recorders (Units in Thousands)

Table 17. Interconnections in Storage Area Networks (Units in Thousands)

Table 18. Interconnections in the Automotive Industry (Units in Thousands)

Table 19. Interconnections Used in Communications Boards (Units in Thousands)

Table 20. Products Using PCI and PCI-X (Units in Thousands)

Table 21. Products Using PCI Express (Units in Thousands)

Table 22. Products Using HyperTransport (Units in Thousands)

Table 23. Products Using Serial RapidIO (Units in Thousands)




List of Figures




Figure 1. Number of Devices Using Non-Proprietary IO (Units in Thousands), 2004-2010

Figure 2. Where Interconnects Belong

Figure 3. A History of PCI and PCI-X Standards, 1992-Present

Figure 4. PCI Express Roadmap

Figure 5. Common Partners in Torrenza Platform

Figure 6. Celoxica RCHTX Card for High Performance Computing

Figure 7. Tundra Semiconductors Tsi109 Host Bridge

interconnect

Abstract

Non-proprietary I/O is seeing an increasing presence within the central processing, printed circuit board, and IP communities. HyperTransport, PCI Express, and RapidIO benefit from the strength of central special interest groups (SIG). The SIG becomes the central point of aggregation for improving I/O standards. HyperTransport 3.0 increased frequency from 1.4GHz per trace line to 2.6GHz per line. PCI Express, the standard which currently has a 2.0 revision before its membership, increases the effective frequency from 2.5GHz to 5GHz. Serial RapidIO also has a 2.0 revision before its members that increases frequency from 3.125Gbaud to 6.25Gbaud.

The increased bandwidths serve to make the I/O more functional, but the non-proprietary I/O is stretching out to new usages. In PCI Express 2.0, the PCI-SIG is developing standards for cabling as well as defining single-root virtualization I/O. With HyperTransport 3.0, methods for power consumption as well as for cabling are introduced. The RapidIO Trade Association, for Serial RapidIO 2.0, helped to define a new Management and Flow Control mechanism that can process payloads of as many as 64KB from 64,000 different senders.

This In-Stat report examines what the implications of changes in the I/O means on a device level. For example, the I/O requirements are different for portable devices than for personal computers. The usages of HyperTransport, PCI Express, and RapidIO are forecast for devices from 2004-2010.

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