I/O, I/O, How Much Faster Can We Go: Chip-to-Chip Interconnects : Market Research Report

I/O, I/O, How Much Faster Can We Go: Chip-to-Chip Interconnects

Published by: In-Stat

Published: Sep. 19, 2005 - 53 Pages

Table
of Contents

Executive Summary

Introduction

Methodology

Technology Overview
- HyperTransport
- PCI and PCI-X
- PCI Express
- RapidIO
- Comparisons
  of Interconnect Technologies
- Brief Notations
  About Proprietary Interconnects

Case Studies
- HyperTransport
- PCI Express
- RapidIO

Product Overview
- HyperTransport
- PCI Express
- RapidIO
- Interfaces
  By Application
  - Computing
  - Networking
  - Telecommuting
  - Consumer
    Electronics
  - Further
    Into the Ecosystem

Report Summary

List
of Tables

Table 1. Summary
Market Forecast for HyperTransport, PCI Express, and RapidIO. 2003-2009
(Units in Thousands)

Table 2. Range
of Throughput (MBps) Offered by HyperTransport, Assuming That Links
in Each Direction are Same Width

Table 3. Range
of Throughput (GBps) and Originating Standards PCI and PCI-X

Table 4. Range
of Throughput (MBps) Offered by PCI Express, Derived by Adding Available
Throughput for Each Direction

Table 5. Range
of Throughput (MBps) Offered by RapidIO

Table 6. A Top-Level
Comparison of HyperTransport, PCI Express and RapidIO

Table 7. Signal
Pin-Counts for the Different Interconnect Standards

Table 8. Forecast
of Worldwide PC shipments with HyperTransport: 2003-2009 (Units in Thousands)

Table 9. Forecast
of Worldwide Server shipments with HyperTransport: 2003-2009 (Units
in Thousands)

Table 10. Forecast
of Worldwide PC shipments with PCI Express: 2003-2009 (Units in Thousands)

Table 11. Forecast
of Worldwide PC shipments with PCI: 2003-2009 (Units in Thousands)

Table 12. Forecast
of Worldwide Server shipments with PCI-X and PCI Express: 2003-2009
(Units in Thousands)

Table 13. Forecast
of Edge and Core Routers with HyperTransport: 2003-2009 (Units in Thousands)

Table 14. Forecast
of Worldwide new W-CDMA channels with RapidIO Interfaces: 2003-2009
(Units in Thousands)

Table 15. Forecast
of Worldwide Videogame Consoles with HyperTransport, 2003-2009

Table 16. Summary
Forecast of Worldwide HyperTransport, RapidIO, and PCI Express Systems,
2003-2009 (Units in Thousands)

List
of Figures

Figure 1. Basic
HyperTransport Performance Characteristics

Figure 2. A History
of PCI and PCI-X Standards 1992-Present

Figure 3. 4-Way
AMD Opterons on an iWill Motherboard

Figure 4. Case
Study of Rambus PCI Express Serial Link Applications

Figure 5. System
Block Diagram Where Both HyperTransport and PCI Express Are Used

Abstract

Chip-to-chip interconnections will not get the attention that central processing units or memory systems will, in regard to extending performance in processor systems. Nonetheless, at all points in a system, the overall performance of the process is affected by its weakest elements. As processor capacity continued to grow and memory caches grew as well, the possibility of bottlenecks increased. In many cases the bottlenecks were caused by the system architecture within the interface.

Several factors contributed to the development of standard interconnections. Market conditions helped to define a spirit of cooperation. Standard interconnection is a platform for individual companies to build upon. By utilizing a common interconnection, companies can devote more resources toward building differentiators at the edge of an application. An added benefit to working with common industry interconnections is that interoperability with common components is assured — an advantage when working with OEMs.

This In-Stat report identifies three emerging chip-to-chip interconnections: HyperTransport, PCI Express, and RapidIO. The origins and evolution of each interconnection is reviewed. Technical barriers and interconnection roadmaps are included and lastly, forecasts are made about the proliferation of interconnection technologies within selected market applications.

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I/O, I/O, How Much Faster Can We Go: Chip-to-Chip Interconnects

Table of Contents

Abstract